1. Field of the Invention
This invention relates to clock generator circuits employed within microprocessing units and more particularly to the testing of delay chains incorporated within microprocessor clock generators. The invention also relates to the testing of electrical delay circuits which have controllable delay characteristics.
2. Description of the Relevant Art
Most microprocessors include an on-chip clock generator circuit for synthesizing internal clock signals. One important requirement is that the internal clock signals be associated with very stable frequency and duty cycle characteristics. Within one exemplary microprocessor clock generator, this is achieved by using a plurality of identical variable delay elements coupled in series to form a delay chain from which timing reference signals may be derived. The timing reference signals are used to trigger transitions in a generated clock signal. Within such clock generators, it is important that the relative delays of the variable delay elements be essentially identical to achieve a desired duty cycle of 50 percent. Accordingly, it may be desirable to test the variable delay elements to determine whether they actually have essentially identical delays.
Although it is relatively simple to fabricate virtually identical delay elements on a single integrated circuit chip, batch-to-batch variations due to processing variations make it very difficult to fabricate a delay element in which a certain control input value will always yield the same fixed time delay. Fortunately, with respect to the above-mentioned clock signal generators, it is only necessary that the relative delays of the variable delay elements within a particular clock generator be essentially identical. The actual delay values are not critical. In view of this, it may not be possible or may not be cost-effective to test this class of delay element by simple comparison with a known reference delay.
A further consideration with respect to the test of delay elements within clock generator circuits is the type of possible defect. In an integrated circuit manufacturing test, it is assumed that the fundamental design of the delay element is sound and that only failures introduced by manufacturing defects remain. A manufacturing defect will not necessarily cause the delay element to fail entirely but may rather subtly or dramatically affect the relationship between the control input and the time delay of the delay element. Complete failure of the delay element is easily detected, but subtle manufacturing defects in delay elements are very difficult to detect.
Accordingly, a test configuration and method are desirable wherein variably controlled delay elements embodied within a microprocessor clock generator may be readily tested for subtle defects without the need for costly calibration of individual delay elements.